![]() Since `define is compiler directive, it can be used across multiple files. This compiler directive is used for defining text MACROS this is normally defined in verilog file "name.vh", where name can be the module that you are coding. You can use the `include compiler directive to include global or commonly-used definitions and tasks, without encapsulating repeated code within module boundaries. The compilation proceeds as though the contents of the included source file appear in place of the `include command. The `include compiler directive lets you insert the entire contents of a source file into another file during Verilog compilation. For specific compiler directives, please refer to simulator manuals. Below we will see some standard and common compiler directives. ![]() This appendix presents those directives that are part of IEEE-1364.Īs in any language, each compiler has its own way of handling command line options and supported compiler directives in code. Compiler directives may appear anywhere in the source description, but it is recommended that they appear outside a module declaration. ![]() ![]() A directive is effective from the point at which it is declared to the point at which another directive overrides it, even across file boundaries. The grave accent mark, `, denotes a compiler directive. A compiler directive may be used to control the compilation of a Verilog description.
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